Exemplary embodiments of the present invention relate to a semiconductor integrated device, and more particularly, to a command control circuit for synchronizing a command signal with a clock and outputting the synchronized command signal.
Conventional electronic devices include semiconductor integrated devices (a circuit). For example, a personal computer, a television set, an audio device, and a communication device include semiconductor integrated devices. The semiconductor integrated devices receive data from other electronic devices or electronic elements, store the received data, and provide the stored data to other electronic devices or electronic elements.
Such a semiconductor integrated device performs an operation in response to a command and an address command generated from an external memory controller. The semiconductor integrated device controls related operations by synchronizing the command and the address command to a clock. Therefore, the semiconductor integrated device internally performs a process of synchronizing an input signal to a clock signal.
FIG. 1 is a diagram illustrating a command control circuit used in a semiconductor integrated device according to the related art.
As shown in FIG. 1, the command control circuit according to the related art is configured to synchronize a command signal CMD that is input to a clock signal CLOCK using a plurality of latches 10 to 18. That is, the command control circuit according to the related art includes a plurality of latches 10 to 18. Each of the plurality of latches 10 to 18 includes a clock end CE for receiving a clock signal, an input end D for receiving an input signal, and an output end Q for outputting a latched signal. The input end D of the first latch 10 receives a command signal CMD. The input end D of the next latch 12 receives an output signal from output end Q of the previous latch 10 as an input signal. Accordingly, the input signal passes sequentially through the plurality of latches.
The output end Q of each latch 10 to 16 is connected to the input end D of the next latch and also connected to an output terminal OUT through selection switches 20-26. The output end Q of latch 18 is connected to the output terminal OUT through selection switch 28. The selection switches 20 to 28 are configured to be controlled in response to selection control signals SELECT<0> to SELECT<4> from a controller (not shown).
FIG. 2 is a diagram illustrating one of the plurality of latches illustrated in FIG. 1. That is, each one of the latches 10 to 18 includes two three-phase inverters 50 and 52. An input end of one of the three phase inverters is connected to an output end of the other. The input signal provided to input end D passes through the three phase inverters 50 and 52 during an enable period when a clock signal CLOCK is in a logic low state and inverted and outputted from an inverter 60.
In the command control circuit according to the related art, a command signal CMD is inputted to the first latch 10 among the plurality of latches and synchronized with a clock signal. Then, the synchronized signal is transferred to the second latch 12. The synchronized command passes sequentially from the second latch 12 to the last latch 18 by the above described operation.
The controller (not shown) enables a selection switch connected to an output end of a corresponding latch to output only an output signal of a latch delayed by the desired number of clocks among the output signals of the plurality of latches 10 to 18. The output signal passes through the selection switch and is outputted through the output terminal OUT.
For example, in case of delaying a signal by two clocks, a command signal CMD is inputted to the first latch 10. The first latch 10 delays the command signal by one clock and outputs the one clock delayed command signal. The one clock delayed command signal from the first latch 10 is transferred to the second latch 12. The second latch 12 delays the received command signal by one clock again. Then, the selection switch 22 is enabled to transfer the output signal of the second latch 12 to the output terminal OUT. For example, in case of delaying a signal by three clocks, a command signal CMD is inputted to the first latch 10. The first latch 10 delays the command signal by one clock. The first latch 10 outputs one clock delayed command signal to the second latch 12. The second latch 12 delays the command signal by one clock again. Then, the second latch 12 outputs the delayed command signal to the third latch 14 and the third latch 14 delays the command signal by one clock again. Then, the selection switch 24 is enabled to transfer the output signal of the third latch 14 to the output terminal OUT.
As shown, all output ends Q of the latches 10 to 18 are connected to one output terminal OUT in the command control circuit of the semiconductor integrated device according to the related art. Accordingly, significant load is applied to the output terminal OUT. Due to the significant load, an output signal of each latch may not be accurately outputted at a desired time. As a result, unnecessary delay may be generated.